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mcm69l736a ? mcm69l818a 1 motorola fast sram advance information 4m late write hstl the mcm69l736a/818a is a 4m synchronous late write fast static ram designed to provide high performance in secondary cache and atm switch, telecom, and other high speed memory applications. the mcm69l818a (organized as 256k words by 18 bits) and the mcm69l736a (organized as 128k words by 36 bits) are fabricated in motorola's high performance silicon gate bicmos technology. the differential clock (ck) inputs control the timing of read/write operations of the ram. at the rising edge of ck, all addresses, write enables, and synchronous selects are registered. an internal buffer and special logic enable the memory to accept write data on the rising edge of ck a cycle after address and control signals. read data is available at the falling edge of ck. the ram uses hstl inputs and outputs. the adjustable input trippoint (v ref ) and output voltage (v ddq ) gives the system designer greater flexibility in optimizing system performance. the synchronous write and byte enables allow writing to individual bytes or the entire word. the impedance of the output buffers is programmable, allowing the outputs to match the impedance of the circuit traces which reduces signal reflections. ? byte write control ? single 3.3 v +10%, 5% operation ? hstl e i/o (jedec standard jesd86 class i) ? hstl e user selectable input trippoint ? hstl e compatible programmable impedance output drivers ? register to latch synchronous operation ? asynchronous output enable ? boundary scan (jtag) ieee 1149.1 compatible ? differential clock inputs ? optional x18 or x36 organization ? mcm69l736a/818a7.5 = 7.5 ns mcm69l736a/818a8.5 = 8.5 ns mcm69l736a/818a9.5 = 9.5 ns mcm69l736a/818a10.5 = 10.5 ns ? 119 bump, 50 mil (1.27 mm) pitch, 14 mm x 22 mm plastic ball grid array (pbga) package this document contains information on a new product. specifications and information herein are subject to change without notice. order this document by mcm69l736a/d semiconductor technical data mcm69l736a mcm69l818a zp package pbga case 99901 4/3/97 ? motorola, inc. 1997
mcm69l736a ? mcm69l818a 2 motorola fast sram functional block diagram address registers sa ck sw sbx control logic data in register memory array g sw registers data out latch dq ss ss registers pin assignments mcm69l736a 6 5 4 3 2 17 b c v ss g a d e f h j v ss v ss sbb v ss sa v ss v ss v ss sa sa sa sa sa sa sa sa nc sa sa nc nc nc dqb sa sa nc zz sw dqa dqa v ddq v ddq dqb v ddq dqb dqb dqa dqa v ss v dd tdo sa tdi tms nc tck dqd dqd v ss sa ck v dd dqa dqa sa v ss dqd dqd v ddq dqd v ss nc dqa dqa sba sbd dqd dqd dqd dqd v ss ck v ss dqc dqa v dd v ref v dd v ref v dd v ddq dqc v ss nc dqb dqb dqb nc sbc dqc dqc v ddq dqc v ss g dqb ss v ss dqc dqc dqc v ss zq dqb v dd nc nc nc sa nc nc k l m n p r t u v ddq v ddq nc v ddq v ddq nc 6 5 4 3 2 17 b c v ss g a d e f h j v ss v ss v ss v ss sa v ss v ss v ss sa sa sa sa sa sa sa sa sa sa sa sa nc nc nc sa sa nc zz sw nc nc v ddq v ddq nc v ddq dqa dqa dqa dqa v ss v dd tdo nc tdi tms nc tck nc dqb v ss sa ck v dd nc dqa sa v ss nc dqb v ddq dqb v ss nc nc dqa sba v ss nc dqb nc dqb v ss ck v ss dqb nc v dd v ref v dd v ref v dd v ddq nc v ss nc dqa dqa nc nc sbb dqb nc v ddq nc v ss g nc ss v ss dqb nc dqb nc v ss zq dqa v dd nc nc nc sa nc nc k l m n p r t u v ddq v ddq nc v ddq v ddq nc mcm69l818a dqc top view
mcm69l736a ? mcm69l818a 3 motorola fast sram mcm69l736a pin descriptions pbga pin locations symbol type description 2a, 3a, 5a, 6a, 3b, 5b, 2c, 3c, 5c, 6c, 4n, 4p, 2r, 6r, 3t, 4t, 5t sa input synchronous address inputs: registered on the rising clock edge. 4k ck input address, data in, and control input register clock. active high. 4l ck input address, data in, and control input register clock. active low. 4m sw input synchronous write: registered on the rising clock edge, active low. writes all enabled bytes. 5l, 5g, 3g, 3l (a), (b), (c), (d) sbx input synchronous byte write enable: enables writes to byte x in conjunction with the sw input. has no effect on read cycles, active low. 4e ss input synchronous chip enable: registered on the rising clock edge, active low. 4f g input output enable: asynchronous pin, active low. 2u tms input test mode select (jtag). 3u tdi input test data in (jtag). 4u tck input test clock (jtag). 5u tdo output test data out (jtag). 4d zq input programmable output impedance: programming pin. 7t zz input reserved for future use. must be grounded. (a) 6k, 7k, 6l, 7l, 6m, 6n, 7n, 6p, 7p (b) 6d, 7d, 6e, 7e, 6f, 6g, 7g, 6h, 7h (c) 1d, 2d, 1e, 2e, 2f, 1g, 2g, 1h, 2h (d) 1k, 2k, 1l, 2l, 2m, 1n, 2n, 1p, 2p dqx i/o synchronous data i/o. 3j, 5j v ref supply input reference: provides reference voltage for input buffers. 4c, 2j, 4j, 6j, 4r, 3r v dd supply core power supply. 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7u v ddq supply output power supply: provides operating power for output buffers. 3d, 5d, 3e, 5e, 3f, 5f, 3h, 5h, 3k, 5k, 3m, 5m, 3n, 5n, 3p, 5p, 5r v ss supply ground. 4a, 1b, 2b, 4b, 6b, 7b, 1c, 7c, 4g, 4h, 1r, 7r, 1t, 2t, 6t, 6u nc e no connection: there is no connection to the chip.
mcm69l736a ? mcm69l818a 4 motorola fast sram mcm69l818a pin descriptions pbga pin locations symbol type description 2a, 3a, 5a, 6a, 3b, 5b, 2c, 3c, 5c, 6c, 4n, 4p, 2r, 6r, 2t, 3t, 5t, 6t sa input synchronous address inputs: registered on the rising clock edge. 4k ck input address, data in, and control input register clock. active high. 4l ck input address, data in, and control input register clock. active low. 4m sw input synchronous write: registered on the rising clock edge, active low. writes all enabled bytes. 5l, 3g (a), (b) sbx input synchronous byte write enable: enables writes to byte x in conjunction with the sw input. has no effect on read cycles, active low. 4e ss input synchronous chip enable: registered on the rising clock edge, active low. 2u tms input test mode select (jtag). 3u tdi input test data in (jtag). 4u tck input test clock (jtag). 5u tdo output test data out (jtag). 4d zq input programmable output impedance: programming pin. 4f g input output enable: asynchronous pin, active low. 7t zz input reserved for future use. must be grounded. (a) 6d, 7e, 6f, 7g, 6h, 7k, 6l, 6n, 7p (b) 1d, 2e, 2g, 1h, 2k, 1l, 2m, 1n, 2p dqx i/o synchronous data i/o. 3j, 5j v ref supply input reference: provides reference voltage for input buffers. 4c, 2j, 4j, 6j, 4r, 3r v dd supply core power supply. 1a, 7a, 1f, 7f, 1j, 7j, 1m, 7m, 1u, 7u v ddq supply output power supply: provides operating power for output buffers. 3d, 5d, 3e, 5e, 3f, 5f, 5g, 3h, 5h, 3k, 5k, 3l, 3m, 5m, 3n, 5n, 3p, 5p, 5r v ss supply ground. 4a, 1b, 2b, 4b, 6b, 7b, 1c, 7c, 2d, 7d, 1e, 6e, 2f, 1g, 4g, 6g, 2h, 4h, 7h, 1k, 6k, 2l, 7l, 6m, 2n, 7n, 1p, 6p, 1r, 7r, 1t, 4t, 6u nc e no connection: there is no connection to the chip.
mcm69l736a ? mcm69l818a 5 motorola fast sram absolute maximum ratings (voltages referenced to v ss , see note 1) rating symbol value unit core supply voltage v dd 0.5 to + 4.6 v output supply voltage v ddq 0.5 to v dd + 0.5 v voltage on any pin v in 0.5 to v dd + 0.5 v input current (per i/o) i in 50 ma output current (per i/o) i out 70 ma power dissipation (see note 2) p d e w operating temperature t a 0 to + 70 c temperature under bias t bias 10 to + 85 c storage temperature t stg 55 to + 125 c notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended oper- ating conditions. exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. power dissipation capability will be dependent upon package characteristics and use environment. see enclosed thermal impedance data. pbga package thermal characteristics rating symbol max unit notes junction to ambient (still air) r q ja 53 c/w 1, 2 junction to ambient (@200 ft/min) single layer board r q ja 38 c/w 1, 2 junction to ambient (@200 ft/min) four layer board r q ja 22 c/w junction to board (bottom) r q jb 14 c/w 3 junction to case (top) r q jc 5 c/w 4 notes: 1. junction temperature is a function of onchip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per semi g3887. 3. indicates the average thermal resistance between the die and the printed circuit board. 4. indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec883 method 1012.1). this device contains circuitry to protect the inputs against damage due to high static volt- ages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maxi- mum rated voltages to this highimpedance circuit. this bicmos memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established. this device contains circuitry that will ensure the output devices are in highz at power up.
mcm69l736a ? mcm69l818a 6 motorola fast sram dc operating conditions and characteristics (0 c t a 70 c, unless otherwise noted) recommended operating conditions (see notes 1 through 4) parameter symbol min typical 7.5 typical 8.5 typical 9.5 typical 10.5 max unit notes input reference dc voltage v ref (dc) 0.6 e e e e 1.1 v 11 core power supply voltage v dd 3.15 e e e e 3.6 v output driver supply voltage v ddq 1.4 e e e e 1.6 v active power supply current (x18) (x36) i dd1 e e 300 390 290 380 270 360 260 350 450 560 ma 5 quiescent active power supply current) i dd2 e 190 190 190 190 250 ma 6, 10 active standby power supply current i sb1 e 160 160 160 160 250 ma 7 quiescent standby power supply current i sb2 e 140 140 140 140 230 ma 8, 10 sleep mode power supply current i sb3 e tbd tbd tbd tbd tbd ma 9, 10 notes: 1. all data sheet parameters specified to full range of v dd unless otherwise noted. all voltages are referenced to voltage applied to v ss bumps. 2. supply voltage applied to v dd connections. 3. supply voltage applied to v ddq connections. 4. all power supply currents measured with outputs open or deselected. 5. v dd = v dd (max), t khkh = t khkh (min), ss registered active, 50% read cycles. 6. v dd = v dd (max), t khkh = dc, ss registered active. 7. v dd = v dd (max), t khkh = t khkh (min), ss registered inactive. 8. v dd = v dd (max), t khkh = dc, ss registered inactive, zz low. 9. v dd = v dd (max), t khkh = dc, registered inactive, zz high. 10. 200 mv v in v ddq 200 mv. 11. although considerable latitude in the selection of the nominal dc value (i.e., rms value) of v ref is supported, the peak to peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . dc input characteristics parameter symbol min max unit notes dc input logic high v ih (dc) v ref + 0.1 v dd + 0.3 v dc input logic low v il (dc) 0.3 v ref 0.1 v 1 input reference dc voltage v ref (dc) 0.6 1.1 v 2 input leakage current i lkg(1) e 5 m a 3 clock input signal voltage v in 0.3 v dd + 0.3 v clock input differential voltage v dif (dc) 0.1 v dd + 0.6 v 4 clock input common mode voltage range (see figure 3) v cm (dc) 0.68 1.1 v 5 clock input crossing point voltage range v x 0.68 1.1 v notes: 1. inputs may undershoot to 0.5 v (peak) for up to 20% t khkh (e.g., 2 ns at a clock cycle time of 10 ns). 2. although considerable latitude in the selection of the nominal dc value (i.e., rms value) of v ref is supported, the peaktopeak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 3. 0 v v in v ddq for all pins. 4. minimum instantaneous differential input voltage required for differential input clock operation. 5. maximum rejectable common mode input voltage variation.
mcm69l736a ? mcm69l818a 7 motorola fast sram dc output buffer characteristics programmable impedance pushpull output buffer mode (0 c t a 70 c, unless otherwise noted, see notes 5 and 6) parameter symbol min max unit notes output logic low v ol v ddq /2 0.025 v ddq /2 +0.025 v 1 output logic high v oh v ddq /2 0.025 v ddq /2 + 0.025 v 2 light load output logic low v ol 1 v ss 0.2 v 3 light load output logic high v oh 1 v ddq 0.2 v ddq v 4 notes: 1. i ol = (v ddq /2)/(rq/5) for values of rq = 175 w rq 350 w. 2. | i oh | = (v ddq /2)/(rq/5) for values of rq = 175 w rq 350 w. 3. i ol 100 m a. 4. | i oh | 100 m a. 5. the impedance controlled mode is expected to be used in pointtopoint applications, driving high impedance inputs. 6. the zq pin is connected through rq to v ss for the controlled impedance mode. dc output buffer characteristics e minimum impedance pushpull output buffer mode (0 c t a 70 c, zq = v dd ) (see notes 1 and 2) parameter symbol min max unit notes output logic low v ol 2 v ss 0.4 v 3 output logic high v oh 2 v ddq 0.4 v ddq v 4 light load output logic low v ol 3 v ss 0.2 v 5 light load output logic high v oh 3 v ddq 0.2 v ddq v 6 notes: 1. the pushpull output mode is expected to be used in bussed applications and may be series or parallel terminated. conforms to the jedec standard jesd86 class i. 2. the zq pin is connected to v dd to enable the minimum impedance mode. 3. i ol 8 ma. 4. ? i oh ? 8 ma. 5. i ol 100 m a. 6. ? i oh ? 100 m a. capacitance (f = 1.0 mhz, dv = 3.0 v, 0 c t a 70 c, periodically sampled rather than 100% tested) characteristic symbol typ max unit input capacitance c in 4 5 pf input/output capacitance c i/o 7 8 pf ck, ck capacitance c ck 4 5 pf
mcm69l736a ? mcm69l818a 8 motorola fast sram ac operating conditions and characteristics (0 c t a 70 c, unless otherwise noted) input pulse levels 0.25 to 1.25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 1 v/ns (20% to 80%) . . . . . . . . . . . . . . . . . . . . . . input timing measurement reference level 0.75 v . . . . . . . . . . . . . . output timing reference level 0.75 v . . . . . . . . . . . . . . . . . . . . . . . . . clock input timing reference level differential crosspoint . . . . . . rq for 50 w impedance 250 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . read/write cycle timing (see note 3) mcm69l736a7.5 mcm69l818a7.5 mcm69l736a8.5 mcm69l818a8.5 mcm69l736a9.5 mcm69l818a9.5 mcm69l736a10.5 mcm69l818a10.5 parameter symbol min max min max min max min max unit notes cycle time t khkh 7 e 8 e 9 e 10 e ns clock high pulse width t khkl 2.8 e 3.2 e 3.6 e 4 e ns clock low pulse width t klkh 2.8 e 3.2 e 3.6 e 4 e ns clock high to output valid t khqv e 7.5 e 8.5 e 9.5 e 10.5 ns 2 clock low to output valid t klqv e 3.5 e 4 e 4 e 4 ns 2 clock low to output hold t klqx 0.5 e 0.5 e 0.5 e 0.5 e ns 2 clock low to output lowz t klqx1 1 e 1 e 1 e 1 e ns 3 clock high to output highz t khqz e 3.5 e 4 e 4 e 4 ns 3 output enable low to output lowz t glqx 0.5 e 0.5 e 0.5 e 0.5 e ns 3 output enable low to output valid t glqv e 3.5 e 4 e 4 e 4 ns 2 output enable to output hold t ghqx 0.5 e 0.5 e 0.5 e 0.5 e ns 2 output enable high to output highz t ghqz e 3.5 e 4 e 4 e 4 ns 3 setup times: address data in chip select write enable t avkh t dvkh t svkh t wvkh 0.5 e 0.5 e 0.5 e 0.5 e ns hold times: address data in chip select write enable t khax t khdx t khsx t khwx 1 e 1 e 1 e 1 e ns notes: 1. measured at 200 mv from steady state. 2. in no case may control input signals (e.g., ss ) be operated with pulse widths less than the minimum clock input pulse width specifications (e.g., t khkl ) or at frequencies that exceed the applied k clock frequency. 3. tested per ac test load diagram. see figure 1. the table of timing values shows either a minimum or a maximum limit for each parameter. input requirements are specified from the external system point of view. thus, ad- dress setup time is shown as a minimum since the system must supply at least that much time. on the other hand, re- sponses from the memory are specified from the device point of view. thus, the access time is shown as a maximum since the device never provides data later than that time. timing limits device under test zq 50 w 50 w 0.75 v v ddq /2 v ref 250 w figure 1. ac test load
mcm69l736a ? mcm69l818a 9 motorola fast sram ac input characteristics parameter symbol min max notes ac input logic high (see figure 4) v ih (ac) v ref + 200 mv ac input logic low (see figures 2 and 4) v il (ac) v ref 200 mv 1 input reference peak to peak ac voltage v ref (ac) 5% v ref (dc) 2 clock input differential voltage v dif (ac) 400 mv v ddq + 600 mv 3 notes: 1. inputs may undershoot to 0.5 v (peak) for up to 20% t khkh (e.g., 2 ns at a clock cycle time of 10 ns). 2. although considerable latitude in the selection of the nominal dc value (i.e., rms value) of v ref is supported, the peak to peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 3. minimum instantaneous differential input voltage required for differential input clock operation. v oh v ss 50% 100% 20% t khkh figure 2. undershoot voltage crossing point v ddq v ss v tr v dif v cp v cm * figure 3. differential inputs/common mode input voltage *v cm , the common mode input voltage, equals v tr ((v tr v cp )/2). v ih (ac) v ref v il (ac) figure 4. differential inputs/common mode input voltage
mcm69l736a ? mcm69l818a 10 motorola fast sram t khkl t khkh dq ck q0 sa a0 a1 register latch readwriteread cycles t klkh q1 q3 t klqv a2 a3 a4 t wvkh t khwx t svkh t khsx t avkh t khax ss sw sbx g t dvkh q4 d2 t khqv t klqx t khdx read read write read read t khqz t klqx1 deselect (highz) t klqx1 t khqz
mcm69l736a ? mcm69l818a 11 motorola fast sram register latch readwriteread cycles (g controlled) dq ck q0 sa a0 a1 q1 q3 a2 a3 a4 ss sw sbx g q4 d2 t glqx read read write read read t ghqz t glqv deselect (highz) t ghqx
mcm69l736a ? mcm69l818a 12 motorola fast sram functional operation read and write operations all control signals except g are registered on the rising edge of ck. these signals must meet the setup and hold times shown in the ac characteristics table. on the falling edge of the current cycle, the output latch becomes trans- parent and data is available. the output data is latched on the rising edge of the next clock. the output data is available at the output at t klqv or t khqv , whichever is later. t khqv is the internal latency of the device. during this same cycle, a new read address can be applied to the address pins. a write cycle can occur on the next cycle as long as t klqx and t dvkh are met. read cycles may follow write cycles immediately. g , ss , and sw control output drive. chip deselect via a high on ss at the rising edge of ck has its effect on the out- put drivers immediately. sw low deselects the output drivers immediately (on the same cycle). output selecting via a low on ss and high on sw at a rising ck has its effect on the output drivers at t klqx . output drive is also controlled direct- ly by output enable (g ). g is an asynchronous input. no clock edges are required to enable or disable the output with g . output data will be valid at t glqv , t khqv , or t klqv, which is even later. outputs will begin driving at t klqx1 . outputs will hold previous data until t klqx or t ghqx . write and byte write functions note that in the following discussion the term abyteo refers to nine bits of the ram i/o bus. in all cases, the timing pa- rameters described for synchronous write input (sw ) apply to each of the byte write enable inputs (sba , sbb , etc.). byte write enable inputs have no effect on read cycles. this allows the system designer not interested in performing byte writes to connect the byte enable inputs to active low (v ss ). reads of all bytes proceed normally and write cycles, activated via a low on sw and the rising edge of ck, write the entire ram i/o width. this way the designer is spared having to drive multiple write input buffer loads. byte writes are performed using the byte write enable in- puts in conjunction with the synchronous write input (sw ). it is important to note that writing any one byte will inhibit a read of all bytes at the current address. the ram cannot simulta- neously read one byte and write another at the same ad- dress. a write cycle initiated with none of the byte write enable inputs active is neither a read or a write. no write will occur, but the outputs will be deselected as in a normal write cycle. late write the write address is sampled on the first rising edge of clock, and write data is sampled on the following rising edge. the late write feature is implemented with single stage write buffering. write buffering is transparent to the user. a comparator monitors the address bus and, when necessary, routes buffer contents to the outputs to ensure coherent op- eration. this occurs in all cases whether there is a byte write or a full word is written. programmable impedance operation the designer can program the rams output buffer imped- ance by terminating the zq pin to v ss through a precision resistor (rq). the value of rq is five times the output imped- ance desired. for example, 250 w resistor will give an output impedance of 50 w . impedance updates occur continuously and the frequency of the update is based on the subdivided k clock. note that if the k clock stops so does the impedance update. the actual change in the impedance occurs in small incre- ments and is monotonic. there are no significant distur- bances that occur on the output because of this smooth update method. the impedance update is not related to any particular type of cycle because the impedance is updated continuously and is based on the k clock. updates occur regardless of wheth- er the the device is performing a read, write or a deselect cycle and does not depend on the state of g . at power up, the output impedance defaults to approxi- mately 50 ohms. it will take 4,000 to 16,000 cycles for the im- pedance to be completely updated if the programmed impedance is much higher or lower than 50 w . the output buffers can also be programmed in a minimum impedance configuration by connecting zq to v dd . power up and initialization once supplies have reached specification levels, a minimum dwell of 1.0 m s with ck inputs cycling is required before beginning normal operations. at power up the output impedance will be set at approximately 50 w , however, in order to match the programmed impedance the part requires deselect cycles to occur.
mcm69l736a ? mcm69l818a 13 motorola fast sram serial boundary scan test access port operation overview the serial boundary scan test access port (tap) on this ram is designed to operate in a manner consistent with ieee 1149.11990 (commonly referred to as jtag), but does not implement all of the functions required for 1149.1 compliance. certain functions have been modified or elimi- nated because their implementation places extra delays in the rams critical speed path. nevertheless, the ram sup- ports the standard tap controller architecture. the tap con- troller is the state machine that controls the tap operation and can be expected to function in a manner that does not conflict with the operation of devices with ieee 1149.1 compliant taps. the tap operates using conventional jedec standard 81b low voltage (3.3 v) ttl/cmos logic level signaling. disabling the test access port it is possible to use this device without utilizing the tap. to disable the tap controller without interfering with normal operation of the device, tck must be tied to v ss to preclude midlevel inputs. tdi and tms are designed so an undriven input will produce a response identical to the application of a logic one, and may be left unconnected. but they may also be tied to v dd through a 1 k resistor. tdo should be left unconnected. tap dc operating characteristics (0 c t a 70 c, unless otherwise noted) parameter symbol min max unit notes logic input logic high v ih 1 2.0 v dd + 0.3 v logic input logic low v il 1 0.3 0.8 v logic input leakage current i lkg e 5 m a 1 cmos output logic low v ol 1 e 0.2 v 2 cmos output logic high v oh 1 v dd 0.2 e v 3 ttl output logic low v ol 2 e 0.4 v 4 ttl output logic high v oh 2 2.4 e v 5 notes: 1. 0 v v in v ddq for all logic input pins. 2. i ol 1 100 m a @ v ol = 0.2 v. sampled, not 100% tested. 3. ? i oh 1 ? 100 m a @ v ddq 0.2 v. sampled, not 100% tested. 4. i ol 2 8 ma @ v ol = 0.4 v. 5. ? i oh 2 ? 8 ma @ v oh = 2.4 v.
mcm69l736a ? mcm69l818a 14 motorola fast sram tap ac operating conditions and characteristics (0 c t a 70 c, unless otherwise noted) input pulse levels 0 to 3.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input rise/fall time 1 v/ns (20% to 80%) . . . . . . . . . . . . . . . . . . . . . . input timing measurement reference level 1.5 v . . . . . . . . . . . . . . . output timing reference level 1.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . output test load 50 w parallel terminated tline with 20 pf . . . . . . receiver input capacitance test load termination supply voltage (v t ) 1.5 v . . . . . . . . . . . . . . . tap controller timing parameter symbol min max unit notes cycle time t thth 100 e ns clock high time t thtl 40 e ns clock low time t tlth 40 e ns tms setup t mvth 10 e ns tms hold t thmx 10 e ns tdi valid to tck high t dvth 10 e ns tck high to tdi don't care t thdx 10 e ns capture setup t cs 10 e ns 1 capture hold t ch 10 e ns 1 tck low to tdo unknown t tlqx 0 e ns tck low to tdo valid t tlov e 20 ns note: 1. t cs + t ch defines the minimum pause in ram i/o pad transitions to ensure accurate pad data capture. ac test load device under test 50 w 50 w 1.5 v tap controller timing diagram t thdx t tlqv t tlqx t dvth t tlth t thmx t mvth t thth test clock (tck) test mode select (tms) test data in (tdi) test data out (tdo) t thtl
mcm69l736a ? mcm69l818a 15 motorola fast sram test access port pins tck e test clock (input) clocks all tap events. all inputs are captured on the rising edge of tck and all outputs propagate from the falling edge of tck. tms e test mode select (input) the tms input is sampled on the rising edge of tck. this is the command input for the tap controller state machine. an undriven tms input will produce the same result as a log- ic one input level. tdi e test data in (input) the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers placed between tdi and tdo. the register placed between tdi and tdo is deter- mined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (see figure 6). an undriven tdi pin will produce the same result as a logic one input level. tdo e test data out (output) output that is active depending on the state of the tap state machine (see figure 6). output changes in response to the falling edge of tck. this is the output side of the serial registers placed between tdi and tdo. trst e tap reset this device does not have a trst pin. trst is optional in ieee 1149.1. the testlogic reset state is entered while tms is held high for five rising edges of tck. power on reset cir- cuitry is included internally. this type of reset does not affect the operation of the system logic. the reset affects test logic only. test access port registers overview the various tap registers are selected (one at a time) via the sequences of ones and zeros input to the tms pin as the tck is strobed. each of the tap registers are serial shift reg- isters that capture serial input data on the rising edge of tck and push serial data out on the subsequent falling edge of tck. when a register is selected it is aplacedo between the tdi and tdo pins. instruction register the instruction register holds the instructions that are executed by the tap controller when it is moved into the run test/idle or the various data register states. the instructions are three bits long. the register can be loaded when it is placed between the tdi and tdo pins. the instruction regis- ter is automatically preloaded with the idcode instruction at powerup or whenever the controller is placed in testlogic reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed through the rams tap to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is identical in length to the number of active input and i/o connections on the ram (not counting the tap pins). this also includes a number of place holder locations (always set to a logic one) reserved for den- sity upgrade address pins. there are a total of 70 bits in the case of the x36 device and 51 bits in the case of the x18 de- vice. the boundary scan register, under the control of the tap controller, is loaded with the contents of the ram i/o ring when the controller is in capturedr state and then is placed between the tdi and tdo pins when the controller is moved to shiftdr state. several tap instructions can be used to activate the boundary scan register. the bump/bit scan order tables describe which device bump connects to each boundary scan register location. the first column defines the bit's position in the boundary scan register. the shift register bit nearest tdo (i.e., first to be shifted out) is defined as bit 1. the second column is the name of the input or i/o at the bump and the third column is the bump number. identification (id) register the id register is a 32bit register that is loaded with a de- vice and vendor specific 32bit code when the controller is put in capturedr state with the idcode command loaded in the instruction register. the code is loaded from a 32bit onchip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when the controller is moved into shiftdr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. id register presence indicator bit no. 0 value 1 motorola jedec id code (compressed format, per ieee standard 1149.1 1990) bit no. 11 10 9 8 7 6 5 4 3 2 1 value 0 0 0 0 0 0 0 1 1 1 0 reserved for future use bit no. 17 16 15 14 13 12 value x x x x x x device width configuration bit no. 22 21 20 19 18 128k x 36 value 0 0 1 0 0 256k x 18 value 0 0 0 1 1 device depth configuration bit no. 27 26 25 24 23 128k x 36 value 0 0 1 0 1 256k x 18 value 0 0 1 1 0 revision number bit no. 31 30 29 28 value x x x x figure 5. id register bit meanings
mcm69l736a ? mcm69l818a 16 motorola fast sram mcm69l736a bump/bit scan order bit no. signal name bump id bit no. signal name bump id 1 m2 5r 36 sa 3b 2 sa 4p 37 nc 2b 3 sa 4t 38 sa 3a 4 sa 6r 39 sa 3c 5 sa 5t 40 sa 2c 6 zz 7t 41 sa 2a 7 dqa 6p 42 dqc 2d 8 dqa 7p 43 dqc 1d 9 dqa 6n 44 dqc 2e 10 dqa 7n 45 dqc 1e 11 dqa 6m 46 dqc 2f 12 dqa 6l 47 dqc 2g 13 dqa 7l 48 dqc 1g 14 dqa 6k 49 dqc 2h 15 dqa 7k 50 dqc 1h 16 sba 5l 51 sbc 3g 17 ck 4l 52 zq 4d 18 ck 4k 53 ss 4e 19 g 4f 54 nc 4g 20 sbb 5g 55 nc 4h 21 dqb 7h 56 sw 4m 22 dqb 6h 57 sbd 3l 23 dqb 7g 58 dqd 1k 24 dqb 6g 59 dqd 2k 25 dqb 6f 60 dqd 1l 26 dqb 7e 61 dqd 2l 27 dqb 6e 62 dqd 2m 28 dqb 7d 63 dqd 1n 29 dqb 6d 64 dqd 2n 30 sa 6a 65 dqd 1p 31 sa 6c 66 dqd 2p 32 sa 5c 67 sa 3t 33 sa 5a 68 sa 2r 34 nc 6b 69 sa 4n 35 sa 5b 70 m1 3r mcm69l818a bump/bit scan order bit no. signal name bump id bit no. signal name bump id 1 m2 5r 36 sbb 3g 2 sa 6t 37 zq 4d 3 sa 4p 38 ss 4e 4 sa 6r 39 nc 4g 5 sa 5t 40 nc 4h 6 zz 7t 41 sw 4m 7 dqa 7p 42 dqb 2k 8 dqa 6n 43 dqb 1l 9 dqa 6l 44 dqb 2m 10 dqa 7k 45 dqb 1n 11 sba 5l 46 dqb 2p 12 ck 4l 47 sa 3t 13 ck 4k 48 sa 2r 14 g 4f 49 sa 4n 15 dqa 6h 50 sa 2t 16 dqa 7g 51 m1 3r 17 dqa 6f 18 dqa 7e 19 dqa 6d 20 sa 6a 21 sa 6c 22 sa 5c 23 sa 5a 24 nc 6b 25 sa 5b 26 sa 3b 27 nc 2b 28 sa 3a 29 sa 3c 30 sa 2c 31 sa 2a 32 dqb 1d 33 dqb 2e 34 dqb 2g 35 dqb 1h notes: 1. the nc pads listed in this table are indeed no connects, but are represented in the boundary scan register by a aplace holdero bit that is forced to logic one. these pads are reserved for use as address inputs on higher density rams that follow this pad out and scan order standard. 2. ck and ck , are sampled individually. ck is not simply a forced complement of the ck input. in scan mode these differential inputs are refer- enced to v ref , not each other. 3. zq, m1, and m2 are not ordinary inputs and may not respond to standard i/o logic levels. zq, m1, and m2 must be driven to within 100 mv of a v dd or v ss supply rail to ensure consistent results. 4. zz must remain at v il during boundary scan to ensure consistent results.
mcm69l736a ? mcm69l818a 17 motorola fast sram tap controller instruction set overview there are two classes of instructions defined in ieee stan- dard 1149.11990, the standard (public) instructions and de- vice specific (private) instructions. some public instructions are mandatory for ieee 1149.1 compliance. optional public instructions must be implemented in prescribed ways. although the tap controller in this device follows the ieee 1149.1 conventions, it is not ieee 1194.1 compliant because some of the mandatory instructions are not fully imple- mented. the tap on this device may be used to monitor all input and i/o pads, but cannot be used to load address, data, or control signals into the ram or to preload the i/o buffers. in other words, the device will not perform ieee 1149.1 extest, intest, or the preload portion of the sample/ preload command. when the tap controller is placed in captureir state, the two least significant bits of the instruction register are loaded with 01. when the controller is moved to the shiftir state, the instruction register is placed between tdi and tdo. in this state, the desired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions, the tap executes newly loaded instructions only when the controller is moved to updateir state. the tap instruction sets for this device are listed in the following tables. standard (public) instructions bypass the bypass instruction is loaded in the instruction regis- ter when the bypass register is placed between tdi and tdo. this occurs when the tap controller is moved to the shiftdr state. this allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. sample/preload sample/preload is an ieee 1149.1 mandatory public instruction. when the sample/preload instruction is loaded in the instruction register, moving the tap controller into the capturedr state loads the data in the ram's input and i/o buffers into the boundary scan register. because the ram clock(s) are independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring con- tents while the input buffers are in transition (i.e., in a metast- able state). although allowing the tap to sample metastable inputs will not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the tap's input data capture setup plus hold time (t cs plus t ch ). the ram's clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. moving the controller to shiftdr state then places the boundary scan register between the tdi and tdo pins. because the preload portion of the command is not im- plemented in this device, moving the controller to the updatedr state with the sample/preload instruction loaded in the instruction register has the same effect as the pausedr command. this functionality is not ieee 1149.1 compliant. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instruction register, whatever length it may be in the device, is loaded with all logic zeros. extest is not implemented in this device. therefore, this device is not ieee 1149.1 compliant. nevertheless, this ram tap does respond to an all zeros instruction, as follows. with the extest (000) instruction loaded in the instruction register, the ram responds just as it does in response to the sample/preload instruction described above, except the ram outputs are forced to highz any time the instruction is loaded. idcode the idcode instruction causes the id rom to be loaded into the id register when the controller is in capturedr mode and places the id register between the tdi and tdo pins in shiftdr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the testlogicreset state. device specific (public) instruction samplez if the samplez instruction is loaded in the instruction register, all ram outputs are forced to an inactive drive state (highz) and the boundary scan register is connected be- tween tdi and tdo when the tap controller is moved to the shiftdr state. device specific (private) instruction no op do not use these instructions; they are reserved for future use.
mcm69l736a ? mcm69l818a 18 motorola fast sram standard (public) instruction codes instruction code* description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all ram outputs to highz state. not ieee 1149.1 compliant. idcode 001** preloads id register and places it between tdi and tdo. does not affect ram operation. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect ram operation. does not implement ieee 1149.1 preload function. not ieee 1149.1 compliant. bypass 111 places bypass register between tdi and tdo. does not affect ram operation. samplez 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all ram output drivers to highz state. * instruction codes expressed in binary; msb on left, lsb on right. ** default instruction automatically loaded at powerup and in testlogicreset state. standard (private) instruction codes instruction code* description no op 011 do not use these instructions; they are reserved for future use. no op 101 do not use these instructions; they are reserved for future use. no op 110 do not use these instructions; they are reserved for future use. * instruction codes expressed in binary; msb on left, lsb on right. capturedr exit1dr exit2dr updatedr captureir exit1ir exit2ir updateir shiftir pauseir shiftdr pausedr testlogic reset runtest/ idle select drscan select irscan 1 0 1 1 1 1 1 1 1 11 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 note: the value adjacent to each state transition represents the signal present at tms at the rising edge of tck. 0 figure 6. tap controller state diagram
mcm69l736a ? mcm69l818a 19 motorola fast sram ordering information (order by full part number) mcm 69l818a xx x x motorola memory prefix part number full part numbers e mcm69l736azp7.5 mcm69l736azp8.5 mcm69l736azp9.5 mcm69l736azp10.5 mcm69l818azp7.5 mcm69l818azp8.5 mcm69l818azp9.5 mcm69l818azp10.5 mcm69l736azp7.5r mcm69l736azp8.5r mcm69l736azp9.5r mcm69l736azp10.5r mcm69l818azp7.5r mcm69l818azp8.5r mcm69l818azp9.5r mcm69l818azp10.5r r = tape and reel, blank = tray package (zp = pbga) speed (7.5 = 7.5 ns, 8.5 = 8.5 ns, 9.5 = 9.5 ns, 10.5 = 10.5 ns) 69l736a
mcm69l736a ? mcm69l818a 20 motorola fast sram zp package 7 x 17 bump pbga case 99901 package dimensions l a b c d e f g h j k l m n p r t u a p n 4x 16x 119x top view k bottom view side view b s 0.20 (0.008) r 6x g g 7654321 d l 0.30 (0.012) s tw ss 0.10 (0.004) s t 0.15 (0.006) t 0.25 (0.010) t 0.35 (0.014) t e c dim a min max min max inches 14.00 bsc 0.551 bsc millimeters b 22.00 bsc 0.866 bsc c 2.40 0.094 d 0.60 0.90 0.024 0.035 e 0.50 0.70 0.020 0.028 f 1.30 1.70 0.051 0.067 g 1.27 bsc 0.050 bsc k 0.80 1.00 0.031 0.039 n 11.90 12.10 0.469 0.476 p 19.40 19.60 0.764 0.772 r 7.62 bsc 0.300 bsc s 20.32 bsc 0.800 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. pin 1a identifier f w t motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, 6f seibubutsuryucenter, p.o. box 5405, denver, colorado 80217. 3036752140 or 18004412447 3142 tatsumi kotoku, tokyo 135, japan. 81335218315 mfax ? : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 internet : http://motorola.com/sps mcm69l736a/d ?

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